Re: [802.3_NGECDC] [YANG for 802.3] Clause 30 modelling assumptions Thread Links Date Links Thread Prev Thread Next Thread Index Date Prev Date Next Date Index Re: [802.3_NGECDC] [YANG for 802.3] Clause 30 modelling assumptions To : STDS-802-3-NGECDC@xxxxxxxxxxxxxxxxx Subject : Re: [802.3_NGECDC] [YANG for 802.3] Clause 30 modelling assumptions From : Edwin Mallette < edwin.mallette@xxxxxxxxx > Date : Fri, 5 Feb 2016 12:28:58 -0500 Delivered-to : mhonarc@xxxxxxxxxxxxxxxx In-reply-to : <027101d15f83$be8cd470$3ba67d50$@gmail.com> List-help : < https://listserv.ieee.org/cgi-bin/wa?

At the time the concept was of a bussed MII with multiple PHYs present, but only one active.  

At the time the concept was of a bussed MII with multiple PHYs present, but only one active.  

Thoughts on the 800 Gb/s and 1.6 Tb/s PCS Thoughts on the 800 Gb/s and 1.6 Tb/s PCS P802.3df Task Force, 03 February 2022 Tom Huber (Nokia) Steve Trowbridge (Nokia) 1 FEC for 800G and 1.6T interfaces • While 802.3bs initially specified a single RS(544,514) FEC code, this has evolved to include additional FEC codes in subsequent projects • It is almost certain that multiple FEC codes will be selected for 800 Gb/s and 1.6 Tb/s operation by P802.3df and follow-on projects at these rates • While RS(544,514) may be adequate for early-adopter PHYs with 100 Gb/s lanes, higher coding-gain FEC may be required for PHYs with 200 Gb/s lanes.

At the time the concept was of a bussed MII with multiple PHYs present, but only one active.  

At the time the concept was of a bussed MII with multiple PHYs present, but only one active.  

* Real measurements of real components (more than simple resistors) * Will signal to noise be acceptable for 1 mA and 100 mV max, with leakages?

At the time the concept was of a bussed MII with multiple PHYs present, but only one active.  

MainTable IEEE 802.3au (IEEE P802.3-2005/Cor 1) D1.1 DTE Power Isolation Corrigendum Comments Response # 1Cl 33 SC 33.4.1 P 14 L 29 Comment Type ER I could only find one place wher the base text needs to be changed to be consistent with published standard.

This is assuming all 10 (100 GE) or 4 (40 GE) SerDes in same chip – This should potentially introduce only a small amount of skew quantified by the uncertainty on the FIFO reset mechanism and de/serializer-related skew – There should be no skew in the stages feeding the Tx FIFOs – Total amount of TX skew should be in the order of 1.8 ns for reset/serializer uncertainty and another 0.2 ns for skew induced from driver/package, total of upto 2 ns – Numbers for RX side are also in the order of upto 2 ns 8 PCS/MLD skew – FPGA case MLD i/f TX PCS/MLD FPGA 10 or 4 lanes @10G PMA/PMD 10G SerDes Core logic 10G SerDes 10 or 4 10G SerDes 10G SerDes 10 or 4 RX 10 or 4 lanes @10G 16b @644M 644M SerDes (x16) 644M SerDes (x16) 644M SerDes (x16) 644M SerDes (x16) 64b @160M 64b @160M 64b @160M 64b @160M 16b @644M 16b @644M 16b @644M MLD i/f: 10 lanes for 100 GE or 4 lanes for 40GE @10G 9 PCS/MLD skew – FPGA case FPGA solution with external 10G SerDes devices – Since current FPGA technology does not support 10G links (SerDes), board level solutions need to connect a MAC/PCS FPGA to 10 (100 GE) or 4 (40 GE) 10G SerDes devices – Assuming a 16-bit i/f between FPGA and external 10G SerDes: still need internal FPGA SerDes to convert from a wide databus to serial 644 Mb/s (16 of them per 10G) – a 4-bit or 2-bit i/f are alternative options – Stages feeding the internal SerDes can introduce upto 12.8 ns (2x64 bits) of skew – Number of pins and internal FPGA SerDes required might prohibit single-FPGA device implementation for 100GE, unless narrower external busses are used (RXAUI for example) 10 PCS/MLD skew (TX and RX), cont. - FPGA FPGA solution with external 10G SerDes devices (cont.) – External SerDes devices are difficult to synchronize, so skew can be introduced by different fill levels in their FIFOs – with a FIFO size of 8 by 16 bits, could have a skew of 7*1.6 ns = 11.2 ns (applies to Tx, no FIFO in Rx) – Add in upto 1.5 ns max for serializer skew – In Rx, no FIFO is needed, deserializer skew can be upto 1.5 ns – Do not expect electrical skew in a 16-bit clocked i/f @644M between FPGA and external SerDes 11 MLD interface Electrical skew (TX and RX) – Calculation of skew requires modeling using controlled impedance traces on standard FR4 low-cost PCBs – A good starting point would be the XFI interface for a chip to chip interconnect • current XFI i/f allows for 9.6dB of loss @5.5GHz • allows for a range from 1” to 8-10” typically 12 MLD i/f Electrical skew (TX and RX) (cont.) – If we assume a 10” range then the upper bound of skew is 10’’, which translates into 10*220ps/in = 2.2ns, so 4.4 ns for TX and RX – Could never happen ☺☺☺☺ – A more realistic scenario would be 1-2” of board skew, 2” translates to 0.88 ns – PCB designers could give more accurate skew data, depends on board size, number of layers etc – Propose a generous 4” of trace length difference allowance, equates to 1.76 ns for both RX and TX 13 PMD/PMA skew (TX and RX), 4x25G MLD protocol supports bit muxing at the MLD i/f as well as at the line side PMA is a simple bit MUX/DeMUX – internal skew should be less than 0.4 ns (per chip, per direction), including analog and digital skew PMA to PMD connection – Traces should in any case be carefully laid out – Should be less than 1” (per direction), which is 0.45 ns (RX and TX) 14 Transmission skew Dependent on PMD type For an SMF optical solution, a 10Km range has a max skew @1300 nm of 1.7ns for transmission skew (4x25G or 4x10G case) For a parallel fiber MMF case @850nm, assuming 44.3ps/m skew accumulation, a 100m range results in 4.43 ns of skew Objective for copper is 10m, therefore the skew contribution should be smaller than the optical cases Not a current objective, but if in the future a 80 km solution is used, then 80 km @ 1550 nm (800 GHz spacing in C band, 4x25G) would result in a 33.2 ns skew 15 Max skew budget – 40GE In all modes: – TX electrical (FPGA): 25.5+0.88+0.62 = 27 ns – RX electrical (FPGA): 14.3+0.88+0.62 = 15.8 ns – TX+RX electrical (FPGA) = 42.8 ns 10Km SMF, CWDM mode – Optical interface (1300 nm, 4x10G): 1.7ns – TOTAL: 42.8 + 1.7 = 44.5 ns 100m MMF, parallel fibers – Optical interface (850 nm): 4.43ns – TOTAL: 42.8 + 4.43 = 47.23 ns 300m MMF, parallel fibers (not an objective) – Optical interface (850 nm): 13.29ns – TOTAL: 42.8 + 13.29 = 56.09 ns 16 Max skew budget – 100GE In all modes: – TX+RX electrical (FPGA) = 42.8 ns (same as in 40GE) 10Km SMF, CWDM – Optical interface (1300 nm, 4x25G): 1.7ns – TOTAL: 42.8 + 1.7 = 44.5 ns 40Km SMF, DWDM – Optical interface (800 GHz spacing): 0.72ns – TOTAL: 42.8 + 0.72 = 43.52 ns 80Km SMF, DWDM (not an objective) – Optical interface (1550 nm, 800 GHz spacing): 33.14ns – TOTAL: 42.8 + 33.14 = 75.94 ns 100m MMF, parallel fibers – Optical interface (850 nm): 4.5ns – TOTAL: 42.8 + 4.43 = 47.23 ns 300m MMF, parallel fibers (not an objective) – Optical interface (850 nm): 13.29ns – TOTAL: 42.8 + 13.29 = 56.09 ns 17 Summary Table for max skew 2 (ASIC) 12.8+1.5 = 14.3 (FPGA solution) PCS/MLD RX 0.62PMA/PMD TX 1.7 Optical SMF (4x10 or 4x25G @1300nm) 4.43 Parallel Fiber MMF (4x or 10x10G @850nm) Transmission 0.62PMA/PMD RX 0.88Electrical MLD i/f RX 11.43 (ASIC) 47.23 (FPGA solution) TOTAL 0.88Electrical MLD i/f TX 2 (ASIC) 12.8+11.2+1.5 = 25.5 (FPGA solution) Max Skew (ns) for objectives PCS/MLD TX Contributor 18 Proposals for skew contributors Propose a 4” MLD interface board trace skew which results in 1.76 ns skew (total RX+TX) Propose a 1” board trace skew for PMA to PMD electrical skew (0.44 ns total RX+TX) 19 Max Skew budget proposal From summary Table: max_estimated_skew = 47.23 ns (for objectives) Propose allowing for a wide margin – for future technology (80 Km reach e.g. ?)

. * Public Transit Busses, Regional Train Service, S-Bahn Commuter Train* , Rental Car, Ride Share *The stop closest to Estrel Berlin is called Sonnenallee.

. * Public Transit Busses, Regional Train Service, S-Bahn Commuter Train* , Rental Car, Ride Share *The stop closest to Estrel Berlin is called Sonnenallee.

. > > > In actuality, many of the XGXS devices being designed are already being > implemented with the option of bypassing the 8b/10b encoders giving the > parallel busses 10bits per channel plus clock anyway, so the LVDS approach > compares to 42 pins > > on the parallel side of the SERDES anyway in many cases. > > This approach is clean, but the speed of the bus is twice as fast.

. * Public Transit Busses, Regional Train Service, S-Bahn Commuter Train* , Rental Car, Ride Share *The stop closest to Estrel Berlin is called Sonnenallee.

When the packet transitions back to the 1394 network it may use the SYT field directly rather than converting the AVBTP Timestamp provided that the CYCLE_TIMERs on each IEEE-1394 buss are synchronized according to the IEEE 1394.1 bridging specification.

The usual suspects are power supply transients, interference from other busses and signals on board, and finally ground loops in your measurement setup that couple external noise in.

Support addition and removal of a node or set of nodes to a continuously operating powered mixing segment • ODVA Specification: “Installation in UL 508A Industrial Control Panels, UL 845 Motor Control Centers, and similar internal ordinary (non-hazardous) locations on an international basis” • Motor Control Center (MCC) serviceability dictates insertion and removal of nodes in a live system Page 18IEEE P802.3 Maintenance report – July 2008 PlenaryVersion 1.0 IEEE P802.3da 10 Mb/s Single Pair Multidrop Segments Enhancement Task Force – October 6, 2021 Telephonic Interim Page 18 Motor Control Center (MCC) Column Bucket has “service positions” Line (mains) enters MCC and is bussed to Buckets Buckets control power to individual Loads May be fully removed during replacement Bucket An MCC “Lineup” is composed of Columns … … which are composed of Buckets Line, Load, and Network are disconnected Back of Bucket has connections Page 19IEEE P802.3 Maintenance report – July 2008 PlenaryVersion 1.0 IEEE P802.3da 10 Mb/s Single Pair Multidrop Segments Enhancement Task Force – October 6, 2021 Telephonic Interim Page 19 QUESTIONS?

Secretary ***ADDENDUM 1: ALPHABETICAL LIST OF THE 58 ATTENDEES Andersson, Ralph, TDK Semiconductor, 530-478-8400, ralph.andersson@tsc.tdk.com Bohbot, Michel, NORDX/CDT, 514-822-7028, michel.bohbot@nordx.com Booth, Brad, JATO Technologies, 512-407-2135, bbooth@jatotech.com Busse, Robert, Transition Networks, 612-941-7600, robertb@transition.com Campbell, Robert, Lucent, 732-957-2669, rrcampbell@lucent.com Chu, George, Adhoc Technologies, 408-993-9818 x299, george@adhoctech.com Cobb, Terry, Lucent, 619-509-0248, tcobb@ixpres.com Creigh, John, Broadcom, 714-450-8700, jcreigh@broadcom.com Daines, Kevin, Packet Engines Dickens, Erik, Texas Instruments, 972-480-2525, edickens@ti.com Dinh, Thuyen, PCA Electronics, 619-496-9780, thuyen@pca.com DiMinico, Chris, CDT Corp., 800-422-9961, cd@mohawk-cdt.com Dineen, Thomas, LSI Logic, 408-954-3739, dineen@lsil.com Dove, Dan, HP, 916-785-4187, dan_dove@hp.com Eisler, George, Rockwell, 310-459-9225, geisler@aol.com Flatman, Alan LAN Technologies, +44 1260297966, a-flatman@compuserve.com Greiss, Israel, Mysticom, +972-9-8850531, israelg@mysticom.com Guo, Bin, AMD, 408-749-5076, bin.guo@amd.com Hamidy, Farid, Pulse, 619-764-8307, faridhamidy@pulseeng.com Hassoun, Marwan, Rockket Chips, 512-750-8944, marwan@rocketchips.com Hatamian, Mehdi, Broadcom, 714-450-8700, mehdi@broadcom.com Hinrichs, Henry, Pulse, 619-674-8208, henryhinrichs@pulseeng.com Jenkins, Charlie, NEC, 408-588-5709, cjenkins@el.nec.com Jiang, Zhongnong, Texas Instruments, 972-480-3888, zhong@msp.sc.ti.com Jorgensen, Thomas, Intel, +45 44886599, thomas.

.)  Consolidation of legacy in-car networks into the new homogenous Electronic Architecture  Other applications include  Transportation (e.g. trains, busses, airplane cabins, traffic control systems, etc.) and similar applications  Industrial automation solutions using Ethernet for factory and process automation including instrumentation control and measurements.  The 1 Twisted Pair 100 Mbit/s interface will improve the favorable cost balance for in- vehicle applications operating over single twisted pair balanced cabling.

This "bridge" could then be sucked into the chip > holding the MAC as 1GHz+ I/O busses become available.

Of New Hampshire +1 603 862 3332 hsk@iol.unh.edu Joris Wils 3Com +1 508 323 2297 joris_wils@3com.com Steve Adams Intel +1 503 264 4907 steve.adams@intel.com Yaron Nachman Lucent Technologies +972 3 645 8373 ynachman@lucent.com Brian Buckmeier BelFuse +1 619 273 0618 bbuckmeier@belfuse.com Toshio Ooka Sumitomo +1 408 737 8517 ooka@sumitomo.com Karlheinz Schwarz SCC +49 721 684844 Schwarz@SCC-online.de Henry Hinrichs Pulse Engineering +1 858 674 8208 henryhinrichs@pulseeng.com Larry Rubin Level One +1 512 407 2136 lrubin@level1.com April Bergstrom AANetcom +1 610 289 3100 april@aanetcom.com John Kincaid Belden +1 765 983 5332 jkbelden@globalsite.net Hong Yu Lancast +1 603 880 1833 hongyu@lancast.com Robert Campbell Lucent Technologies +1 732 957 2669 rrcampbell@lucent.com John Bestel Lucent Technologies +1 610 712 7790 bestel@lucent.com Curtis Siller Lucent Technologies +1 978 960 1313 csiller@lucent.com Michael A Smith Control Net +1 408 341 1428 michael@controlnet.com Shahab Shahbaz MidCom +1 909 736 8800 SShahbaz@Midcom-inc.com Michel Soerensen Intel michel.soerensen@intel.com Thomas Joergensen Intel +1 454 988 6595 thomas.joergensen@intel.com Robert Busse Transition Networks +1 612 996 1546 robertb@transition.com Khy Vijeh National Semiconductor +1 408 721 3722 khosrow.khy.vijeh@nsc.com Steve Carlson ESTA +1 503 626 4206 scarlson@hspdesign.com Khaled Amer AmerNet +1 949 552 1114 khaledamer@usa.net Steve Dreyer LSI Logic +1 510 226 7400 sdreyer@seeq.com Tom Mathey NDS +1 408 865 1763 tmathey@concentric.net Bill Quackenbush Cisco Systems +1 408 526 4596 wlq@cisco.com Geoff Thompson Nortel +1 408 495 1339 Geoff_Thompson@baynetworks.com Ari Halpern 3Com +972 9 970 7312 Ari_Halpern@3com.com Amir Lehr PowerDsine +972 3 934 7663 amirl@powerdsine.com Nick Stapleton 3Com +44 1442 438092 Nick_Stapleton@3com.com Rami Caspi Siemens +972 4 995 3200 rami@siemensdc.com Carlos Rios 3Com +1 408 326 2844 carlos_rios@3com.com Arlan Anderson Nortel Networks +1 613 763 7868 arlan@nortelnetworks.com Oscar E Agazzi Broadcom +1 949 450 8700 oea@broadcom.com Fred Lucas 3Com +1 410 884 4095 Fred_Lucas@3com.com Scott Fritz TDK Semiconductor +1 530 478 8271 scott.fritz@tsc.tdk.com Scott Burton Mitel Corp +1 613 592 2122 scott_burton@mitel.com Rick Brooks Nortel Networks +1 408 495 1867 ribrooks@nortelnetworks.com Mike Nootbeer TDK Semiconductor +1 530 478 8593 mike.nootbeer@tsc.tdk.com Don Pannell I-Cube +1 408 341 1888 Donp@icube.com Ralph Andersson TDK Semiconductor +1 530 478 8400 ralph.andersson@tsc.tdk.com Robert A J Pieters TDK Semiconductor +1 530 478 8262 robert.pieters@tsc.tdk.com Willem Wery Intel +1 503 264 9873 willem.wery@intel.com Juan Jover Level One +1 305 674 8880 jjover@level1.com Mike McCormack 3Com +1 978 749 0000 mike_s_mccormack@3com.com Daun Langston Fujitsu +1 408 922 9134 daun@compuserve.com David Law 3Com +44 1442 438060 David_Law@3com.com

. > > > In actuality, many of the XGXS devices being designed are already being > implemented with the option of bypassing the 8b/10b encoders giving the > parallel busses 10bits per channel plus clock anyway, so the LVDS approach > compares to 42 pins > > on the parallel side of the SERDES anyway in many cases. > > This approach is clean, but the speed of the bus is twice as fast.

This "bridge" could then be sucked into the chip > holding the MAC as 1GHz+ I/O busses become available.

Cisco Systems 0 1 1 31 Bathrick, Greg PMC-Sierra 0 1 0 10 Beaudoin, Denis Texas Instruments Incorporated Texas Instruments Incorporated 1 1 1 41 Belopolsky, Yakov Self Employed Bel Stewart 1 1 0 20 Bennett, Michael Lawrence Berkeley National Lab Lawrence Berkeley National Lab 1 1 1 30 Booth, Brad Applied Micro (AMCC) AppliedMicro 1 1 0 31 Braun, Ralf-Peter Deutsche Telekom AG Deutsche Telekom AG 1 1 1 41 Brown, Matthew AppliedMicro Applied Micro 1 1 1 41 Bugg, Mark Molex Incorporated 1 1 0 31 Busse, Robert Transition Networks, Inc.

. * Public Transit Busses, Regional Train Service, S-Bahn Commuter Train* , Rental Car, Ride Share *The stop closest to Estrel Berlin is called Sonnenallee.