. • Single channel (0) used to negotiate – Similar to 10GBASE-KR, make AN mandatory at 40G to avoid use of parallel detection • Transmit equalizer training – Re-use 10GBASE-KR training – Mandate inter-lane randomness • The definition of training frame PRBS seeding already does this – Link will not be up until all lanes complete equalizer training • FEC – The FEC is designed as a generic sub-layer below the 10GBASE-R PCS • Provides agnostic transport of 64B/66B code words • Can easily be used with either direct PCS output or striped 64B/66B – Error correction could be difficult to implement at non-striped rates – An Error-correction disabled option would allow FEC coding to be used for alignment without the penalty of FEC correction latency 11 March 2008 5 64B/66B Sync based alignment • The 64B/66B Sync bits can deskew 32UI • Backplane link skew sources – Transmit SERDES – Backplane including connectors – Receive SERDES – Receive re-alignment • This scheme could also be used as the basis of a XLAUI or CAUI extender interface – XLAUI/CAUI will be less demanding than backplane • 10inch, 1 connector vs 40inch 2 connectors 11 March 2008 6 Transmit SERDES skew • With appropriate design SERDES inter-lane transmit skew can be limited to analog skews – <1UI – Need to sync digital stages between lanes • Where this has not been done we have seen up to 4UI of digital skew (in addition to the analog skew) 11 March 2008 7 Backplane skew • Backplane skew is caused by differences in channel length between the channels on – The line card – The connectors – The Backplane • Total backplane channel length is ≤ 40inches (1m) • At 10Gbps 1inch of FR4 has <200ps or ~2UI of delay – 12UI of backplane skew budget would allow for 6inches of channel length variation between channels (15%) – Typical backplane interchannel skew is <1ns (10UI) – Need input from more backplane manufacturers 11 March 2008 8 Receive SERDES skew • Analog skews – <1UI • Quantization skew – Each lane deserializes data into words, each with its own word clock – Even if the word clocks are closely aligned, Sync bits may fall into different words due to other skews • This is seen as an effective skew of the word width • For wide buses, this can be significant (32bit) or prohibitive (64bit) 11 March 2008 9 Alignment skew • SERDES receive data must be gearboxed to the 66bit symbol width and aligned to symbol boundaries – If the gearbox and aligner are not combined then there can be up to 66 bits of quantization skew – If gearbox and aligner are combined the quantization skew is limited to the SERDES word size 11 March 2008 10 Avoiding Quantization skew • SERDES with bus width = 66/n, and “jog” – Aligning the bus width with the symbol width and allowing the deserializer position to be “jogged” removes quantization skew • Commonly used for 8B/10B with a 10bit or 20bit word width. – Unfortunately 11,22,33,or 66bits are not common SERDES bus widths!