And busses are expensive.

For instance, the field does not allow to multicast a control frame to multiple destination busses.

802W-0114-SocialEventSummaryPoster IEEE 802W SOCIAL LUCKY STRIKE BOWLING @ LA LIVE Wednesday January 22nd 6:30 PM – 8:30 PM SHUTTLE BUS STARTS @ 5:45 PM • Busses will be boarded In Front of Hyatt on the Avenue of the Stars • Busses will depart as filled until 6:45 PM • Busses will drop off attendees near the Staples Center approximately 1 block from the bowling alley - a short walk to Lucky Strike is required.

802W-0114-SocialEventSummaryPoster IEEE 802W SOCIAL LUCKY STRIKE BOWLING @ LA LIVE Wednesday January 22nd 6:30 PM – 8:30 PM SHUTTLE BUS STARTS @ 5:45 PM • Busses will be boarded In Front of Hyatt on the Avenue of the Stars • Busses will depart as filled until 6:45 PM • Busses will drop off attendees near the Staples Center approximately 1 block from the bowling alley - a short walk to Lucky Strike is required.

They will have interlocks & > > busses devoted to them.

Best Regards to all, Robert Busse -----Original Message----- From: David_Law@3com.com [ mailto:David_Law@3com.com ] Sent: Wednesday, January 25, 2006 7:42 AM To: Robert Busse Subject: RE: Required comments against IEEE 802.3auDTE Power Isolation cor rigendum Hi Robert, Just wanted to say thank you for your reply.

*SHUTTLE BUS STARTS @ 5:45 PM* * Busses may be boarded In Front of Hyatt on the Avenue of the Stars * Busses will depart as filled until 6:45 PM * Busses will drop off attendees near the Staples Center approximately 1 block from the bowling alley - a short walk to Lucky Strike is required.

Non-power-of-two busses happen all the time.

They will have interlocks & busses devoted to them.

SHUTTLE BUS STARTS @ 5:45 PM * Busses may be boarded In Front of Hyatt on the Avenue of the Stars * Busses will depart as filled until 6:45 PM * Busses will drop off attendees near the Staples Center approximately 1 block from the bowling alley - a short walk to Lucky Strike is required.  

Thanks in advance, Robert Busse Prev by Date: RE: [802.3af] IEE802.3af and IEC60950 - safety issues Next by Date: [802.3af] IEE802.3af and IEC60950 - safety issues Prev by thread: [802.3af] 802.3af PD detection Next by thread: [802.3af] IEE802.3af and IEC60950 - safety issues Index(es): Date Thread

Non-power-of-two busses happen all the time. > > > > Intel is perfectly happy with 80-bit busses to accommodate > > their double extended datatypes.

Non-power-of-two busses happen all the time. >>> >>> Intel is perfectly happy with 80-bit busses to accommodate >>> their double extended datatypes.

My answers (off the top of my head) are: Busses?

T R A N S F O R M I N G H O W C A R S O F T H E F U T U R E A R E B U I L T e T H E R N O V I AⒸ2020 IEEE contribution – 1722b 11 CAN-Busses form Error-Domains.

My answers (off the top of my head) are: Busses?

=0 Gearbox in Time (run faster to have a constant input pattern) 128 width Gearbox in Width (run faster to have a constant input pattern) 136 width Requires Gearbox(es) Requires Multi-clocks Or 3 Build Decoder with continuous input pattern  128 symbol width  Direct interface to PMA and PCS Now working – functionally and FPGA fit FPGA KP4 Resources (ALM ≜ 6LUT) 4 100G KP4 : 19K ALMs  4x100G: 78K ALMs  Improved from November 2014 results 400G KP4 (4 x 136 symbols): 70K ALM 400G KP4 (128 symbol continuous): 70K ALM 1x400G continuous throughput same size as simple input styles  More complex algorithm and logic  Offset by slightly smaller datapath 1x400G slightly smaller than 4x100G FPGA Use Considerations 5 FPGA system implications  Area of 1x400G smaller than 4x100G  But 4x100G has a more decomposable routing congestion Easier to fit automatically, possibly lower speed grade device  Time and cost consideration  Probably not significant reason, especially consideration likely production device technology Routing not so much a problem inside FEC core  Most busses or bus groups smaller than symbol datapath  Bussing can be decomposed inside FEC core  Bigger issue moving data to/from FEC  May indicate similar system concern for any FEC approach (1x400G or 4x100G) FPGA Resource Ratios 6 1M LUT FF FPGA 2016 2M LUT FF FPGA 2016 70K LUT RS DEC 1x400G KP4 decoder fraction of likely target FPGAs Similar area roadmap from all major FPGA manufacturers 1x400GE FEC ASIC 7 ASIC continuous throughput simpler pattern than FPGA continuous throughput  Largely because of 2x clock rate Simpler design  Simpler control structure  Narrower datapaths Designed and Implemented  Shown in breakout presentation Other 8 Does not require additional logic  No duplicated engines Although this is one way of implementing these input patterns  Double syndrome method will add 10%-20% decoder area  Still not a material consideration No architectural difference between ASIC and FPGA approach  Same gate complexity  FPGA has more algorithmic and control complexity ¼ cycle vs. ½ cycle increment Other input patterns can be accomodated  Moving to 96 symbol datapaths for future FPGAs Conclusions 9 1x400G KP4 FEC can be made integration friendly  Direct connect interface with a single clock domain 400G FEC options relatively constant area FPGA fitting may be more difficult at 1x400G  But perhaps not Does not appear to be any material considerations between 1x400G and 4x100G FEC implementations We can choose FEC on what is best for standard moving forward Thank You

They will have interlocks & > busses devoted to them.

Bridging 1394: a requirement for Residential Ethernet Michael Johas Teener Plumblinks mike@teener.com Plumblinks September 28, 2004 Slide 2 Agenda • 1394 use in the home – Why and how – Current and projected market • Networking 1394 busses – Current solutions – Why Ethernet?

IEEE 802.3 VOTERS IN PERIL (10)November 2012 Busse, Robert Ganga, Ilango S.

Applications Local area networks (LANs) implement various network topologies including rings, busses, and stars [1].

Non-power-of-two busses happen all the time. > > Intel is perfectly happy with 80-bit busses to accommodate > their double extended datatypes.

IEEE 802.3 VOTERS IN PERIL (30)July 2011 Abbott, John Beaudoin, Denis Breuer, Dirk Busse, Robert Chang, Frank Chantrell, Thomas Estes, David Firoozmand, Farzin Ganga, Ilango S.

Recovered.PDF 7/4/99802.3 POTENTIAL VOTERS JULY 1999 72 Qualify Azadet, Kameran Belur, Harish Buckman, Lisa Busse, Robert Camacho, David M.

.- My estimated cost is on the order of $63K (Current conversion rates) Here are the calcs and assumptions DAY Num per bus # busses Trips /bus CHF /bus EUR Euros Price $ Monday AM 400 50 8 2 CHF 309.00 189 € 3,021 € $4,484 Monday AM 800 50 16 2 CHF 309.00 189 € 6,042 € $8,967 Tuesday AM 800 50 16 2 CHF 309.00 189 € 6,042 € $8,967 Tuesday PM 800 50 16 2 CHF 309.00 189 € 6,042 € $8,967 Wednesday AM 800 50 16 2 CHF 309.00 189 € 6,042 € $8,967 Wednesday PM 800 50 16 2 CHF 309.00 189 € 6,042 € $8,967 Thursday AM 800 50 16 2 CHF 309.00 189 € 6,042 € $8,967 Thursday PM 400 50 8 2 CHF 309.00 189 € 3,021 € $4,484 If you don't like my numbers you can do your own BUT I think we have to admit that we're looking $50K or more for busses AND even then it will be an unsatisfactory situation Past plenaries with short bus rides between buildings were unhappy in outcome Rome traffic is legendarily awful.